| Name of HoD | Mr. S. K. Ganesh Kumar Pedapudi |
| Qualification | M.Tech., (Ph.D), |
| Phone Number | +91 94402 45467 |
| Email Address | pganesh66@gmail.com |
| Experience | 14 Years |
Educational Qualification:
- Pursuing research in the Department of Electronics Engineering at Sathyabama Institute of Science & Technology, Chennai
- Master of Technology in VLSI Design, Sathyabama University – I Class
Teaching Experience:
- Associate Professor, Dept of Electronics and Communication Engg., A.M Reddy Memorial College of Engineering & Technology, Petlurivaripalem (July 2019 – Till date)
- GATE Faculty in various Institutions (March 2018 – July 2019)
- Guest Faculty, Dept of Electronics and Communication Engg., JNTUN (July 2017 – March 2018)
- Assistant Professor, Dept of Electronics and Communication Engg., A.M Reddy Memorial College of Engineering & Technology (Jan 2016 – May 2017)
- Assistant Professor, Dept of Electronics and Communication Engg., Kakinada Institute of Engineering & Technology, Korangi, East Godavari Dt (June 2008 – Dec 2015)
International Journal Publications:
- “Low-Testing, Low-Power and High-Speed Implementation of 3-Weight Pattern Generation Based on Accumulator Cell”, International Journal of Advanced Research in Electronics & Communication Engineering, Dec-2013 (ISSN 2278-909X)
- “Implementation of 64-Bit Multiplier Unit Using Modified Wallace Structure”, International Journal of Advanced Technology and Innovative Research, Dec-2014
- “Front Design and Implementation of High Speed Dual-D-FF FIFO synchronizer using Verilog”, International Journal of Engineering and Advanced Technology, Feb-2019 (ISSN: 2249-8958)
- “Implementing And Modelling PWM Control And Its Duty-phase Changes Using Verilog”, International Journal of Advanced Science and Technology, Vol. 29, No.02, 2020, pp. 1508-1516
National Conference Papers Published:
- “VLSI Implementation of Compact Pipelined Low Power Camellia Block Cipher”, National Conference on Advances in Communication & Electrical Engineering, 2011, BVC Odalarevu
- “FPGA Implementation of SHA-1 Algorithm for High Speed Applications”, National Conference on Advances in Communication & Electrical Engineering, 2011, BVC Odalarevu
National Journal Papers Published:
- “Design of 32-Bit RISC CPU Based on MIPS”, National Journal of Global Research in Computer Science, Sept-2011 (ISSN 2229-371X)
Workshops / Seminars Attended:
- Two week ISTE Workshop on Analog Electronics, IIT Kharagpur, 4-14 June 2013, KIET Engineering College, Kakinada
- Seminar on MATLAB & SIMULINK for Engineering Education, Kakinada, March 2013
- Mission 10X Workshop, KIET Engineering College, 29 May – June 2012
- Two week ISTE Workshop on Basic Electronics, IIT Bombay, 28 June – 8 July 2011, KIET Engineering College, Kakinada
Professional Activities:
- Diploma Principal at A.M. REDDY MEMORIAL COLLEGE OF ENGINEERING & TECHNOLOGY (Jan 2015 – May 2016)
- In-charge HoD of ECE Dept., KIET College of Engineering (June 2014 – 2015)
- NBA Accreditation Coordinator, ECE Department, KIET College of Engineering
- Attended HOD meetings and completed assigned tasks by higher authorities
- Seating arrangement and Disciplinary Committee member for Graduation Day (2011, 2012 batches)
- Student counseling and discipline management
- UG Project Coordinator (2010-2011 batch)
- Judge for paper presentations in Technical Fest (2012-2014)
- Produced academic results above 80% each semester
- Guided more than 25 UG/PG projects in ECE/VLSI branches